With advances in integrated circuit design and fabrication, the integration densities of integrated circuit devices such as integrated circuit memory devices continue to increase. Operating voltages of the devices may also decrease. For example, in highly integrated memory devices, an operating voltage may be used in the integrated circuit that is lower than the external power supply voltage.
In order to obtain a stable internal power supply voltage, a reference voltage generator is often provided in an integrated circuit. In order to provide a stable reference voltage, it is generally desirable to provide a reference voltage generator that is relatively impervious to environmental effects that may be caused by operating temperature variations, fabrication process variations and external power supply voltage variations.
FIG. 1 illustrates a conventional reference voltage generator as described in Korean Patent Announcement Gazette, Number 94-7298. As shown in FIG. 1, the reference voltage generator includes first and second complementary field effect transistors 14 and 16 and a pair of resistors 10 and 12.
In particular, as shown in FIG. 1, the gate of N-type Metal Oxide Semiconductor (NMOS) field effect transistor 14 is connected to a reference voltage output terminal Vref that is formed by a first node 11 between resistors 10 and 12. As also shown, resistors 10 and 12 and the controlled electrodes of P-type MOS (PMOS) transistor 16 are connected between first and second power supply voltages Vcc and Vss. The second resistor and the PMOS transistor 16 define a second node 13 therebetween. The gate electrode of PMOS transistor 16 is connected to second node 13. The controlled electrodes of the PMOS transistor 16 are connected between the first node 11 and the second power supply voltage Vss. The substrate of the PMOS transistor 16 is also connected to the output terminal Vref at first node 11.
Analysis of the reference voltage generator of FIG. 1 will now be provided. In response to a power supply voltage Vcc, a current I10 that flows through resistor 10 is divided into current I12 through resistor 12 and current I16 through the channel of the PMOS transistor 16. The value of I10 is given by the following equation: EQU I10=(Vcc-Vref)/R10 (1)
where R10 is the resistance value of resistor 10. Since NMOS transistor 14 is in saturation, I12 is defined by the following equation: EQU I12=(Vref-Vx)/R12=(.beta.n/2)(Vref-Vtn).sup.2 (2)
where Vx and Vtn are the voltage at node 13 and the threshold voltage of transistor 14 respectively, and .beta.n is a constant determined by several factors such as the width and length of the channel of transistor 14, the carrier mobility and the thickness of the gate insulator of transistor 14.
PMOS transistor 16 generally has a large channel width and the voltage level at node 13 is generally lower than the voltage level at node 11 by the threshold voltage of the PMOS transistor 16. Thus, the PMOS transistor generally operates in the subthreshold region. The current I16 that passes through PMOS transistor 16 while in the subthreshold region may be defined as follows: EQU I16=Ido(W/L)EXP[Vg/nVT](EXP[-Vs/VT]-EXP[-Vd/VT]) (3A)
where Ido is constant, W and L are channel width and length, and Vs, Vg and Vd are source-to-bulk voltage, gate-to-bulk voltage and drain-to-bulk voltage, of PMOS transistor 16, respectively. See for example, pages 124-127 of "CMOS Analog Circuit Design" by Phillip E. Allen et al.
If PMOS transistor 16 is operating in a saturation region as is NMOS transistor 14, and the drain-to-source voltage Vds is about 12 volts, then Equation 3A may be reduced to the following equation: EQU I16=Ido(W/L)EXP[(Vref-Vx)/nVT] (3B)
where the exponential terms EXP[-Vs/VT]-EXP[-Vd/VT] become negligible because Vds is about 1.2 volts and is much larger than 3VT, where VT is kT/q. Accordingly, the voltage Vx at second node 13 may be given by: EQU Vx=Vref-((R12(.beta.n/2)(Vref-Vtn).sup.2) (4)
Since I10-I12=I16, the following equation may be obtained: EQU (Vcc-Vref)/R10-(.beta.n/2) (Vref-Vtn).sup.2 =Ido(W/L)EXP[R12(.beta.n/2)(1/nVT)(Vref-Vtn).sup.2 ] (5)
In the reference voltage generator of FIG. 1, NMOS transistor 14 and PMOS transistor 16 may compensate one another relative to variations of the power supply voltage Vcc. In particular, with increasing power supply voltage Vcc, the voltage Vref on first node 11 rises slightly to increase the values (Vcc-Vref)/R10 and (.beta.n/2)(Vref-Vtn).sup.2 of Equation (5). The value of I10, (Vcc-Vref)/R10, increases greatly, while the value of I12, (.beta.n/2)(Vref-Vtn).sup.2, increases slightly. However, the value of the left term of the Equation (5) also increases greatly. Also, in the right term of Equation (5), the increased Vref makes the value of the right term increase greatly so as to equal the value of the left term. FIG. 2 graphically illustrates variations in Vref as a function of variation of the power supply voltage from 2 V to 5 V.
The two transistors 14 and 16 may also compensate one another against temperature variations, as shown in FIG. 3. The overall compensation for variations of power supply voltage and temperature of the circuit of FIG. 1 are cumulatively described in FIG. 4, where plots A, B and C correspond to temperatures of 0.degree. C., 25.degree. C. and 100.degree. C., respectively.
Unfortunately, however, as shown in FIG. 5, the threshold voltages of the NMOS and PMOS transistors 14 and 16 may vary widely due to variations in the fabrication process thereof. Thus, the voltage level on node 11, i.e. Vref, may not be stable, and may not be compensated by the two transistors 14 and 16. For example, FIG. 5 shows that Vref may change by about 0.5 volts when the threshold voltage of the NMOS transistor 14 varies by about .+-.0.05 volts. The CMOS manufacturing environment of the complementary transistors may produce process variations that are even higher, which may render the threshold voltages even more unstable, and which may change the reference voltage Vref even more.